1. Field of the Invention
The present invention relates to a manufacturing method of a semiconductor device and the semiconductor device, and more particularly relates to a manufacturing method of a high-yield semiconductor device and the semiconductor device.
2. Related Background Art
With the recent advance of microfabrication technology, the minimum feature size of a semiconductor device becomes less than 100 nm, and the difficulty level of fabrication increases. A memory cell array of a NAND-type nonvolatile semiconductor memory device out of semiconductor devices has a structure in which the number of contacts per cell is reduced, and hence the layout of a wiring layer for word lines, bit lines, and so on becomes a layout such as line and space with minimum feature size which needs the most advanced microfabrication technology (For example, see Japanese patent Application Laid-open No. 2002-313970).
In the case of the aforementioned layout of the NAND-type nonvolatile semiconductor memory device, in a word line end portion on the side where potential is not lead to the wiring layer above the word line, there is a possibility that resist pattern collapse occurs with the progress of scale-down. It is known that this is caused by pattern thinning of a photoresist due to proximity effect, a problem in terms of shape, or ununiformity of drops of water remaining during rinse drying after development. It is also known that depending on fabrication conditions and processing contents, resist collapse occurs also during etching of a lower film beneath the photoresist with the photoresist as a mask.
This phenomenon has been hitherto handled by thinning the film thickness of the photoresist and so on, but to improve resolution, the film thickness of the photoresist has already been thinned to the limit of film thickness necessary for the fabrication of the lower film beneath the photoresist. Hence, the thickness of the photoresist cannot be easily thinned any more.
Therefore, in Japanese Patent Application Laid-open No. 2004-15056, the occurrence of resist pattern collapse can be prevented by extending an end portion of a word line in area, but an increase in layout pattern is inevitable.
Moreover, the aforementioned problem is not limited to the nonvolatile semiconductor memory device, and also may be a problem for other semiconductor devices.